| Programmer | Languages Used | |||||
|---|---|---|---|---|---|---|
| 1 |
 Sahas Talasila
|
35 mins | 11 mins | TeX, VHDL, XML, SystemVerilog, V, Git Config, Tcl | 🇬🇧 | |
| 2 |
 Praveen Perera
|
1 min | 0 secs | SystemVerilog, Markdown, VHDL, Git Config | hireable | 🇺🇸 |
| 3 |
 Erick Andrés Obregón Fonseca
|
0 secs | 0 secs | SystemVerilog, Python, Markdown, C++, C, Bash, CMake, JSON, Makefile, … | hireable | 🇨🇷 |
